opdracht 3.3 beter
This commit is contained in:
stijn
@@ -3,31 +3,29 @@ opdracht 3.3.elf: file format elf32-avr
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .data 00000002 00800100 00000190 00000224 2**0
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0 .data 00000000 00800100 00800100 00000196 2**0
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CONTENTS, ALLOC, LOAD, DATA
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1 .text 00000190 00000000 00000000 00000094 2**1
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1 .text 00000142 00000000 00000000 00000054 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .bss 00000002 00800102 00800102 00000226 2**0
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ALLOC
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3 .comment 00000030 00000000 00000000 00000226 2**0
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2 .comment 00000030 00000000 00000000 00000196 2**0
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CONTENTS, READONLY
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4 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 00000258 2**2
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3 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 000001c8 2**2
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CONTENTS, READONLY
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5 .debug_aranges 00000038 00000000 00000000 00000294 2**0
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4 .debug_aranges 00000038 00000000 00000000 00000204 2**0
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CONTENTS, READONLY, DEBUGGING
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6 .debug_info 00000944 00000000 00000000 000002cc 2**0
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5 .debug_info 00000944 00000000 00000000 0000023c 2**0
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CONTENTS, READONLY, DEBUGGING
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7 .debug_abbrev 00000878 00000000 00000000 00000c10 2**0
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6 .debug_abbrev 00000878 00000000 00000000 00000b80 2**0
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CONTENTS, READONLY, DEBUGGING
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8 .debug_line 00000329 00000000 00000000 00001488 2**0
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7 .debug_line 00000317 00000000 00000000 000013f8 2**0
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CONTENTS, READONLY, DEBUGGING
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9 .debug_frame 00000074 00000000 00000000 000017b4 2**2
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8 .debug_frame 00000068 00000000 00000000 00001710 2**2
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CONTENTS, READONLY, DEBUGGING
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10 .debug_str 0000046a 00000000 00000000 00001828 2**0
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9 .debug_str 0000046a 00000000 00000000 00001778 2**0
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CONTENTS, READONLY, DEBUGGING
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11 .debug_loc 000000cd 00000000 00000000 00001c92 2**0
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10 .debug_loc 000000b3 00000000 00000000 00001be2 2**0
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CONTENTS, READONLY, DEBUGGING
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12 .debug_ranges 00000028 00000000 00000000 00001d5f 2**0
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11 .debug_ranges 00000028 00000000 00000000 00001c95 2**0
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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@@ -116,20 +114,20 @@ Disassembly of section .text:
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98: 11 e0 ldi r17, 0x01 ; 1
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9a: a0 e0 ldi r26, 0x00 ; 0
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9c: b1 e0 ldi r27, 0x01 ; 1
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9e: e0 e9 ldi r30, 0x90 ; 144
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9e: e2 e4 ldi r30, 0x42 ; 66
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a0: f1 e0 ldi r31, 0x01 ; 1
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a2: 00 e0 ldi r16, 0x00 ; 0
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a4: 0b bf out 0x3b, r16 ; 59
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a6: 02 c0 rjmp .+4 ; 0xac <__do_copy_data+0x14>
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a8: 07 90 elpm r0, Z+
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aa: 0d 92 st X+, r0
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ac: a2 30 cpi r26, 0x02 ; 2
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ac: a0 30 cpi r26, 0x00 ; 0
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ae: b1 07 cpc r27, r17
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b0: d9 f7 brne .-10 ; 0xa8 <__do_copy_data+0x10>
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000000b2 <__do_clear_bss>:
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b2: 21 e0 ldi r18, 0x01 ; 1
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b4: a2 e0 ldi r26, 0x02 ; 2
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b4: a0 e0 ldi r26, 0x00 ; 0
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b6: b1 e0 ldi r27, 0x01 ; 1
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b8: 01 c0 rjmp .+2 ; 0xbc <.do_clear_bss_start>
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@@ -137,11 +135,11 @@ Disassembly of section .text:
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ba: 1d 92 st X+, r1
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000000bc <.do_clear_bss_start>:
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bc: a4 30 cpi r26, 0x04 ; 4
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bc: a0 30 cpi r26, 0x00 ; 0
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be: b2 07 cpc r27, r18
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c0: e1 f7 brne .-8 ; 0xba <.do_clear_bss_loop>
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c2: 5b d0 rcall .+182 ; 0x17a <main>
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c4: 63 c0 rjmp .+198 ; 0x18c <_exit>
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c2: 34 d0 rcall .+104 ; 0x12c <main>
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c4: 3c c0 rjmp .+120 ; 0x13e <_exit>
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000000c6 <__bad_interrupt>:
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c6: 9c cf rjmp .-200 ; 0x0 <__vectors>
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@@ -162,8 +160,8 @@ void wait( int ms ) {
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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ce: ef ec ldi r30, 0xCF ; 207
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d0: f7 e0 ldi r31, 0x07 ; 7
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ce: e3 ec ldi r30, 0xC3 ; 195
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d0: f9 e0 ldi r31, 0x09 ; 9
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d2: 31 97 sbiw r30, 0x01 ; 1
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d4: f1 f7 brne .-4 ; 0xd2 <wait+0xa>
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d6: 00 c0 rjmp .+0 ; 0xd8 <wait+0x10>
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@@ -183,8 +181,8 @@ void wait( int ms ) {
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volatile int msCount = 0;
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void timer2Init( void ) {
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OCR2 = 155; // Compare value of counter 2
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e6: 8b e9 ldi r24, 0x9B ; 155
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OCR2 = 150; //155 // Compare value of counter 2
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e6: 86 e9 ldi r24, 0x96 ; 150
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e8: 83 bd out 0x23, r24 ; 35
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TIMSK |= BIT(7); // T2 compare match interrupt enable
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ea: 87 b7 in r24, 0x37 ; 55
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@@ -192,8 +190,8 @@ void timer2Init( void ) {
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ee: 87 bf out 0x37, r24 ; 55
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sei(); // turn_on intr all
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f0: 78 94 sei
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TCCR2 = 0b00001011; // Initialize T2: timer, prescaler=32, compare output disconnected,CTC,RUN
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f2: 8b e0 ldi r24, 0x0B ; 11
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TCCR2 = 0b00001101; // Initialize T2: timer, prescaler=32, compare output disconnected,CTC,RUN
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f2: 8d e0 ldi r24, 0x0D ; 13
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f4: 85 bd out 0x25, r24 ; 37
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f6: 08 95 ret
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@@ -207,86 +205,58 @@ ISR( TIMER2_COMP_vect ) {
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fc: 0f b6 in r0, 0x3f ; 63
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fe: 0f 92 push r0
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100: 11 24 eor r1, r1
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102: 2f 93 push r18
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104: 3f 93 push r19
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106: 8f 93 push r24
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108: 9f 93 push r25
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msCount++; // Increment ms counter
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10a: 80 91 02 01 lds r24, 0x0102 ; 0x800102 <__data_end>
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10e: 90 91 03 01 lds r25, 0x0103 ; 0x800103 <__data_end+0x1>
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112: 01 96 adiw r24, 0x01 ; 1
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114: 90 93 03 01 sts 0x0103, r25 ; 0x800103 <__data_end+0x1>
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118: 80 93 02 01 sts 0x0102, r24 ; 0x800102 <__data_end>
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if ( msCount >= msThersh ) {
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11c: 20 91 02 01 lds r18, 0x0102 ; 0x800102 <__data_end>
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120: 30 91 03 01 lds r19, 0x0103 ; 0x800103 <__data_end+0x1>
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124: 80 91 00 01 lds r24, 0x0100 ; 0x800100 <__DATA_REGION_ORIGIN__>
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128: 90 91 01 01 lds r25, 0x0101 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
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12c: 28 17 cp r18, r24
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12e: 39 07 cpc r19, r25
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130: d8 f0 brcs .+54 ; 0x168 <__vector_9+0x70>
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// Toggle bit 0 van PORTC
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PORTC ^= BIT(0);
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132: 95 b3 in r25, 0x15 ; 21
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134: 81 e0 ldi r24, 0x01 ; 1
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136: 89 27 eor r24, r25
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138: 85 bb out 0x15, r24 ; 21
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msCount = 0;
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13a: 10 92 03 01 sts 0x0103, r1 ; 0x800103 <__data_end+0x1>
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13e: 10 92 02 01 sts 0x0102, r1 ; 0x800102 <__data_end>
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if(msThersh == 15){
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142: 80 91 00 01 lds r24, 0x0100 ; 0x800100 <__DATA_REGION_ORIGIN__>
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146: 90 91 01 01 lds r25, 0x0101 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
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14a: 0f 97 sbiw r24, 0x0f ; 15
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14c: 39 f4 brne .+14 ; 0x15c <__vector_9+0x64>
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msThersh = 25;
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14e: 89 e1 ldi r24, 0x19 ; 25
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150: 90 e0 ldi r25, 0x00 ; 0
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152: 90 93 01 01 sts 0x0101, r25 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
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156: 80 93 00 01 sts 0x0100, r24 ; 0x800100 <__DATA_REGION_ORIGIN__>
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15a: 06 c0 rjmp .+12 ; 0x168 <__vector_9+0x70>
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102: 8f 93 push r24
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104: 9f 93 push r25
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PORTC ^= BIT(0);
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106: 95 b3 in r25, 0x15 ; 21
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108: 81 e0 ldi r24, 0x01 ; 1
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10a: 89 27 eor r24, r25
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10c: 85 bb out 0x15, r24 ; 21
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if(OCR2 == 250){
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10e: 83 b5 in r24, 0x23 ; 35
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110: 8a 3f cpi r24, 0xFA ; 250
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112: 19 f4 brne .+6 ; 0x11a <__vector_9+0x22>
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OCR2 = 150;
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114: 86 e9 ldi r24, 0x96 ; 150
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116: 83 bd out 0x23, r24 ; 35
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118: 02 c0 rjmp .+4 ; 0x11e <__vector_9+0x26>
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} else {
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msThersh = 15;
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15c: 8f e0 ldi r24, 0x0F ; 15
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15e: 90 e0 ldi r25, 0x00 ; 0
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160: 90 93 01 01 sts 0x0101, r25 ; 0x800101 <__DATA_REGION_ORIGIN__+0x1>
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164: 80 93 00 01 sts 0x0100, r24 ; 0x800100 <__DATA_REGION_ORIGIN__>
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} // Reset ms_count value
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}
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OCR2 = 250;
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11a: 8a ef ldi r24, 0xFA ; 250
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11c: 83 bd out 0x23, r24 ; 35
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}
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}
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168: 9f 91 pop r25
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16a: 8f 91 pop r24
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16c: 3f 91 pop r19
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16e: 2f 91 pop r18
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170: 0f 90 pop r0
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172: 0f be out 0x3f, r0 ; 63
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174: 0f 90 pop r0
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176: 1f 90 pop r1
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178: 18 95 reti
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11e: 9f 91 pop r25
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120: 8f 91 pop r24
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122: 0f 90 pop r0
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124: 0f be out 0x3f, r0 ; 63
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126: 0f 90 pop r0
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128: 1f 90 pop r1
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12a: 18 95 reti
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0000017a <main>:
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0000012c <main>:
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int main( void ) {
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DDRC = 0xFF;
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17a: 8f ef ldi r24, 0xFF ; 255
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17c: 84 bb out 0x14, r24 ; 20
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12c: 8f ef ldi r24, 0xFF ; 255
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12e: 84 bb out 0x14, r24 ; 20
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PORTC = BIT(0); // set PORTC for output (toggle PC0)
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17e: 81 e0 ldi r24, 0x01 ; 1
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180: 85 bb out 0x15, r24 ; 21
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130: 81 e0 ldi r24, 0x01 ; 1
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132: 85 bb out 0x15, r24 ; 21
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timer2Init();
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182: b1 df rcall .-158 ; 0xe6 <timer2Init>
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134: d8 df rcall .-80 ; 0xe6 <timer2Init>
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while (1) {
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// do something else
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wait(10); // every 10 ms (busy waiting
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184: 8a e0 ldi r24, 0x0A ; 10
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186: 90 e0 ldi r25, 0x00 ; 0
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188: 9f df rcall .-194 ; 0xc8 <wait>
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18a: fc cf rjmp .-8 ; 0x184 <main+0xa>
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136: 8a e0 ldi r24, 0x0A ; 10
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138: 90 e0 ldi r25, 0x00 ; 0
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13a: c6 df rcall .-116 ; 0xc8 <wait>
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13c: fc cf rjmp .-8 ; 0x136 <main+0xa>
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0000018c <_exit>:
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18c: f8 94 cli
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0000013e <_exit>:
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13e: f8 94 cli
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0000018e <__stop_program>:
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18e: ff cf rjmp .-2 ; 0x18e <__stop_program>
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00000140 <__stop_program>:
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140: ff cf rjmp .-2 ; 0x140 <__stop_program>
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@@ -8,21 +8,16 @@ S11300503AC0000038C0000036C0000034C00000C0
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S113006032C0000030C000002EC000002CC00000D0
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S11300702AC0000028C0000026C0000024C00000E0
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S113008022C0000020C000001EC0000011241FBEBA
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S1130090CFEFD0E1DEBFCDBF11E0A0E0B1E0E0E9F9
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S11300A0F1E000E00BBF02C007900D92A230B1074F
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S11300B0D9F721E0A2E0B1E001C01D92A430B2075B
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S11300C0E1F75BD063C09CCF20E030E008C0EFECE8
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S11300D0F7E03197F1F700C000002F5F3F4F28177A
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S11300E03907ACF308958BE983BD87B7806887BF70
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S11300F078948BE085BD08951F920F920FB60F92EE
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S113010011242F933F938F939F9380910201909199
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S1130110030101969093030180930201209102014F
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S11301203091030180910001909101012817390752
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S1130130D8F095B381E0892785BB10920301109212
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S1130140020180910001909101010F9739F489E136
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S113015090E0909301018093000106C08FE090E04D
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S113016090930101809300019F918F913F912F9172
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S11301700F900FBE0F901F9018958FEF84BB81E0F6
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S113018085BBB1DF8AE090E09FDFFCCFF894FFCF1E
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S10501900F005A
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S1130090CFEFD0E1DEBFCDBF11E0A0E0B1E0E2E4FC
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S11300A0F1E000E00BBF02C007900D92A030B10751
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S11300B0D9F721E0A0E0B1E001C01D92A030B20761
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S11300C0E1F734D03CC09CCF20E030E008C0E3EC42
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S11300D0F9E03197F1F700C000002F5F3F4F281778
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S11300E03907ACF3089586E983BD87B7806887BF75
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S11300F078948DE085BD08951F920F920FB60F92EC
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S113010011248F939F9395B381E0892785BB83B591
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S11301108A3F19F486E983BD02C08AEF83BD9F91AB
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S11301208F910F900FBE0F901F9018958FEF84BB87
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S113013081E085BBD8DF8AE090E0C6DFFCCFF8948D
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S1050140FFCFEB
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S9030000FC
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@@ -5,7 +5,7 @@
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* Author : Etienne
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*/
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#define F_CPU 8e6
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#define F_CPU 10e6
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#include <avr/io.h>
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#include <util/delay.h>
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#include <avr/interrupt.h>
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@@ -23,26 +23,21 @@ void wait( int ms ) {
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volatile int msCount = 0;
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void timer2Init( void ) {
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OCR2 = 155; // Compare value of counter 2
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OCR2 = 150; //155 // Compare value of counter 2
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TIMSK |= BIT(7); // T2 compare match interrupt enable
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sei(); // turn_on intr all
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TCCR2 = 0b00001011; // Initialize T2: timer, prescaler=32, compare output disconnected,CTC,RUN
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TCCR2 = 0b00001101; // Initialize T2: timer, prescaler=32, compare output disconnected,CTC,RUN
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}
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unsigned int msThersh = 15;
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ISR( TIMER2_COMP_vect ) {
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msCount++; // Increment ms counter
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if ( msCount >= msThersh ) {
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// Toggle bit 0 van PORTC
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PORTC ^= BIT(0);
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msCount = 0;
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if(msThersh == 15){
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msThersh = 25;
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PORTC ^= BIT(0);
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if(OCR2 == 250){
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OCR2 = 150;
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} else {
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msThersh = 15;
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} // Reset ms_count value
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}
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OCR2 = 250;
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}
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}
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int main( void ) {
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