271 lines
8.9 KiB
Plaintext
271 lines
8.9 KiB
Plaintext
|
|
GLCD.elf: file format elf32-avr
|
|
|
|
Sections:
|
|
Idx Name Size VMA LMA File off Algn
|
|
0 .data 00000000 00800100 00800100 00000184 2**0
|
|
CONTENTS, ALLOC, LOAD, DATA
|
|
1 .text 00000130 00000000 00000000 00000054 2**1
|
|
CONTENTS, ALLOC, LOAD, READONLY, CODE
|
|
2 .comment 00000030 00000000 00000000 00000184 2**0
|
|
CONTENTS, READONLY
|
|
3 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 000001b4 2**2
|
|
CONTENTS, READONLY
|
|
4 .debug_aranges 00000040 00000000 00000000 000001f0 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
5 .debug_info 00000a18 00000000 00000000 00000230 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
6 .debug_abbrev 00000882 00000000 00000000 00000c48 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
7 .debug_line 00000369 00000000 00000000 000014ca 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
8 .debug_frame 00000064 00000000 00000000 00001834 2**2
|
|
CONTENTS, READONLY, DEBUGGING
|
|
9 .debug_str 00000463 00000000 00000000 00001898 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
10 .debug_loc 000000f4 00000000 00000000 00001cfb 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
11 .debug_ranges 00000030 00000000 00000000 00001def 2**0
|
|
CONTENTS, READONLY, DEBUGGING
|
|
|
|
Disassembly of section .text:
|
|
|
|
00000000 <__vectors>:
|
|
0: 45 c0 rjmp .+138 ; 0x8c <__ctors_end>
|
|
2: 00 00 nop
|
|
4: 4b c0 rjmp .+150 ; 0x9c <__bad_interrupt>
|
|
6: 00 00 nop
|
|
8: 49 c0 rjmp .+146 ; 0x9c <__bad_interrupt>
|
|
a: 00 00 nop
|
|
c: 47 c0 rjmp .+142 ; 0x9c <__bad_interrupt>
|
|
e: 00 00 nop
|
|
10: 45 c0 rjmp .+138 ; 0x9c <__bad_interrupt>
|
|
12: 00 00 nop
|
|
14: 43 c0 rjmp .+134 ; 0x9c <__bad_interrupt>
|
|
16: 00 00 nop
|
|
18: 41 c0 rjmp .+130 ; 0x9c <__bad_interrupt>
|
|
1a: 00 00 nop
|
|
1c: 3f c0 rjmp .+126 ; 0x9c <__bad_interrupt>
|
|
1e: 00 00 nop
|
|
20: 3d c0 rjmp .+122 ; 0x9c <__bad_interrupt>
|
|
22: 00 00 nop
|
|
24: 3b c0 rjmp .+118 ; 0x9c <__bad_interrupt>
|
|
26: 00 00 nop
|
|
28: 39 c0 rjmp .+114 ; 0x9c <__bad_interrupt>
|
|
2a: 00 00 nop
|
|
2c: 37 c0 rjmp .+110 ; 0x9c <__bad_interrupt>
|
|
2e: 00 00 nop
|
|
30: 35 c0 rjmp .+106 ; 0x9c <__bad_interrupt>
|
|
32: 00 00 nop
|
|
34: 33 c0 rjmp .+102 ; 0x9c <__bad_interrupt>
|
|
36: 00 00 nop
|
|
38: 31 c0 rjmp .+98 ; 0x9c <__bad_interrupt>
|
|
3a: 00 00 nop
|
|
3c: 2f c0 rjmp .+94 ; 0x9c <__bad_interrupt>
|
|
3e: 00 00 nop
|
|
40: 2d c0 rjmp .+90 ; 0x9c <__bad_interrupt>
|
|
42: 00 00 nop
|
|
44: 2b c0 rjmp .+86 ; 0x9c <__bad_interrupt>
|
|
46: 00 00 nop
|
|
48: 29 c0 rjmp .+82 ; 0x9c <__bad_interrupt>
|
|
4a: 00 00 nop
|
|
4c: 27 c0 rjmp .+78 ; 0x9c <__bad_interrupt>
|
|
4e: 00 00 nop
|
|
50: 25 c0 rjmp .+74 ; 0x9c <__bad_interrupt>
|
|
52: 00 00 nop
|
|
54: 23 c0 rjmp .+70 ; 0x9c <__bad_interrupt>
|
|
56: 00 00 nop
|
|
58: 21 c0 rjmp .+66 ; 0x9c <__bad_interrupt>
|
|
5a: 00 00 nop
|
|
5c: 1f c0 rjmp .+62 ; 0x9c <__bad_interrupt>
|
|
5e: 00 00 nop
|
|
60: 1d c0 rjmp .+58 ; 0x9c <__bad_interrupt>
|
|
62: 00 00 nop
|
|
64: 1b c0 rjmp .+54 ; 0x9c <__bad_interrupt>
|
|
66: 00 00 nop
|
|
68: 19 c0 rjmp .+50 ; 0x9c <__bad_interrupt>
|
|
6a: 00 00 nop
|
|
6c: 17 c0 rjmp .+46 ; 0x9c <__bad_interrupt>
|
|
6e: 00 00 nop
|
|
70: 15 c0 rjmp .+42 ; 0x9c <__bad_interrupt>
|
|
72: 00 00 nop
|
|
74: 13 c0 rjmp .+38 ; 0x9c <__bad_interrupt>
|
|
76: 00 00 nop
|
|
78: 11 c0 rjmp .+34 ; 0x9c <__bad_interrupt>
|
|
7a: 00 00 nop
|
|
7c: 0f c0 rjmp .+30 ; 0x9c <__bad_interrupt>
|
|
7e: 00 00 nop
|
|
80: 0d c0 rjmp .+26 ; 0x9c <__bad_interrupt>
|
|
82: 00 00 nop
|
|
84: 0b c0 rjmp .+22 ; 0x9c <__bad_interrupt>
|
|
86: 00 00 nop
|
|
88: 09 c0 rjmp .+18 ; 0x9c <__bad_interrupt>
|
|
...
|
|
|
|
0000008c <__ctors_end>:
|
|
8c: 11 24 eor r1, r1
|
|
8e: 1f be out 0x3f, r1 ; 63
|
|
90: cf ef ldi r28, 0xFF ; 255
|
|
92: d0 e1 ldi r29, 0x10 ; 16
|
|
94: de bf out 0x3e, r29 ; 62
|
|
96: cd bf out 0x3d, r28 ; 61
|
|
98: 40 d0 rcall .+128 ; 0x11a <main>
|
|
9a: 48 c0 rjmp .+144 ; 0x12c <_exit>
|
|
|
|
0000009c <__bad_interrupt>:
|
|
9c: b1 cf rjmp .-158 ; 0x0 <__vectors>
|
|
|
|
0000009e <wait>:
|
|
//is active low (refer to datasheet)
|
|
|
|
|
|
void wait( int ms )
|
|
{
|
|
for (int i=0; i<ms; i++)
|
|
9e: 20 e0 ldi r18, 0x00 ; 0
|
|
a0: 30 e0 ldi r19, 0x00 ; 0
|
|
a2: 08 c0 rjmp .+16 ; 0xb4 <wait+0x16>
|
|
#else
|
|
//round up by default
|
|
__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
|
|
#endif
|
|
|
|
__builtin_avr_delay_cycles(__ticks_dc);
|
|
a4: e3 ec ldi r30, 0xC3 ; 195
|
|
a6: f9 e0 ldi r31, 0x09 ; 9
|
|
a8: 31 97 sbiw r30, 0x01 ; 1
|
|
aa: f1 f7 brne .-4 ; 0xa8 <wait+0xa>
|
|
ac: 00 c0 rjmp .+0 ; 0xae <wait+0x10>
|
|
ae: 00 00 nop
|
|
b0: 2f 5f subi r18, 0xFF ; 255
|
|
b2: 3f 4f sbci r19, 0xFF ; 255
|
|
b4: 28 17 cp r18, r24
|
|
b6: 39 07 cpc r19, r25
|
|
b8: ac f3 brlt .-22 ; 0xa4 <wait+0x6>
|
|
{
|
|
_delay_ms( 1 ); // library function (max 30 ms at 8MHz)
|
|
}
|
|
}
|
|
ba: 08 95 ret
|
|
|
|
000000bc <trigger>:
|
|
|
|
void trigger()
|
|
{
|
|
CONTROLPORT |= GLCD_EN; //EN high
|
|
bc: 88 b3 in r24, 0x18 ; 24
|
|
be: 80 62 ori r24, 0x20 ; 32
|
|
c0: 88 bb out 0x18, r24 ; 24
|
|
#else
|
|
//round up by default
|
|
__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
|
|
#endif
|
|
|
|
__builtin_avr_delay_cycles(__ticks_dc);
|
|
c2: 81 e2 ldi r24, 0x21 ; 33
|
|
c4: 8a 95 dec r24
|
|
c6: f1 f7 brne .-4 ; 0xc4 <trigger+0x8>
|
|
c8: 00 00 nop
|
|
_delay_us(E_DELAY);
|
|
CONTROLPORT &= ~GLCD_EN; //EN low
|
|
ca: 88 b3 in r24, 0x18 ; 24
|
|
cc: 8f 7d andi r24, 0xDF ; 223
|
|
ce: 88 bb out 0x18, r24 ; 24
|
|
d0: 81 e2 ldi r24, 0x21 ; 33
|
|
d2: 8a 95 dec r24
|
|
d4: f1 f7 brne .-4 ; 0xd2 <trigger+0x16>
|
|
d6: 00 00 nop
|
|
d8: 08 95 ret
|
|
|
|
000000da <glcd_on>:
|
|
}
|
|
//----------------------
|
|
void glcd_on()
|
|
{
|
|
#ifdef GLCD_CS_ACTIVE_LOW
|
|
CONTROLPORT &= ~CS1; //Activate both chips
|
|
da: 88 b3 in r24, 0x18 ; 24
|
|
dc: 8e 7f andi r24, 0xFE ; 254
|
|
de: 88 bb out 0x18, r24 ; 24
|
|
CONTROLPORT &= ~CS2;
|
|
e0: 88 b3 in r24, 0x18 ; 24
|
|
e2: 8d 7f andi r24, 0xFD ; 253
|
|
e4: 88 bb out 0x18, r24 ; 24
|
|
#else
|
|
CONTROLPORT |= CS1; //Activate both chips
|
|
CONTROLPORT |= CS2;
|
|
#endif
|
|
CONTROLPORT &= ~GLCD_RS; //RS low --> command
|
|
e6: 88 b3 in r24, 0x18 ; 24
|
|
e8: 8b 7f andi r24, 0xFB ; 251
|
|
ea: 88 bb out 0x18, r24 ; 24
|
|
CONTROLPORT &= ~GLCD_RW; //RW low --> write
|
|
ec: 88 b3 in r24, 0x18 ; 24
|
|
ee: 87 7f andi r24, 0xF7 ; 247
|
|
f0: 88 bb out 0x18, r24 ; 24
|
|
DATAPORT = 0x3F; //ON command
|
|
f2: 8f e3 ldi r24, 0x3F ; 63
|
|
f4: 85 bb out 0x15, r24 ; 21
|
|
trigger();
|
|
f6: e2 cf rjmp .-60 ; 0xbc <trigger>
|
|
f8: 08 95 ret
|
|
|
|
000000fa <glcd_off>:
|
|
}
|
|
//----------------------
|
|
void glcd_off()
|
|
{
|
|
#ifdef GLCD_CS_ACTIVE_LOW
|
|
CONTROLPORT &= ~CS1; //Activate both chips
|
|
fa: 88 b3 in r24, 0x18 ; 24
|
|
fc: 8e 7f andi r24, 0xFE ; 254
|
|
fe: 88 bb out 0x18, r24 ; 24
|
|
CONTROLPORT &= ~CS2;
|
|
100: 88 b3 in r24, 0x18 ; 24
|
|
102: 8d 7f andi r24, 0xFD ; 253
|
|
104: 88 bb out 0x18, r24 ; 24
|
|
#else
|
|
CONTROLPORT |= CS1; //Activate both chips
|
|
CONTROLPORT |= CS2;
|
|
#endif
|
|
CONTROLPORT &= ~GLCD_RS; //DI low --> command
|
|
106: 88 b3 in r24, 0x18 ; 24
|
|
108: 8b 7f andi r24, 0xFB ; 251
|
|
10a: 88 bb out 0x18, r24 ; 24
|
|
CONTROLPORT &= ~GLCD_RW; //RW low --> write
|
|
10c: 88 b3 in r24, 0x18 ; 24
|
|
10e: 87 7f andi r24, 0xF7 ; 247
|
|
110: 88 bb out 0x18, r24 ; 24
|
|
DATAPORT = 0x3E; //OFF command
|
|
112: 8e e3 ldi r24, 0x3E ; 62
|
|
114: 85 bb out 0x15, r24 ; 21
|
|
trigger();
|
|
116: d2 cf rjmp .-92 ; 0xbc <trigger>
|
|
118: 08 95 ret
|
|
|
|
0000011a <main>:
|
|
int main(void)
|
|
{
|
|
while (1)
|
|
{
|
|
|
|
glcd_on();
|
|
11a: df df rcall .-66 ; 0xda <glcd_on>
|
|
wait(2000);
|
|
11c: 80 ed ldi r24, 0xD0 ; 208
|
|
11e: 97 e0 ldi r25, 0x07 ; 7
|
|
glcd_off();
|
|
120: be df rcall .-132 ; 0x9e <wait>
|
|
wait(2000);
|
|
122: eb df rcall .-42 ; 0xfa <glcd_off>
|
|
124: 80 ed ldi r24, 0xD0 ; 208
|
|
126: 97 e0 ldi r25, 0x07 ; 7
|
|
128: ba df rcall .-140 ; 0x9e <wait>
|
|
12a: f7 cf rjmp .-18 ; 0x11a <main>
|
|
|
|
0000012c <_exit>:
|
|
12c: f8 94 cli
|
|
|
|
0000012e <__stop_program>:
|
|
12e: ff cf rjmp .-2 ; 0x12e <__stop_program>
|