GLCD driver begin
This commit is contained in:
Guilliam Lutz
270
Microcontrollers/GLCD/Debug/GLCD.lss
Normal file
270
Microcontrollers/GLCD/Debug/GLCD.lss
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@@ -0,0 +1,270 @@
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GLCD.elf: file format elf32-avr
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .data 00000000 00800100 00800100 00000184 2**0
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CONTENTS, ALLOC, LOAD, DATA
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1 .text 00000130 00000000 00000000 00000054 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .comment 00000030 00000000 00000000 00000184 2**0
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CONTENTS, READONLY
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3 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 000001b4 2**2
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CONTENTS, READONLY
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4 .debug_aranges 00000040 00000000 00000000 000001f0 2**0
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CONTENTS, READONLY, DEBUGGING
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5 .debug_info 00000a18 00000000 00000000 00000230 2**0
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CONTENTS, READONLY, DEBUGGING
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6 .debug_abbrev 00000882 00000000 00000000 00000c48 2**0
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CONTENTS, READONLY, DEBUGGING
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7 .debug_line 00000369 00000000 00000000 000014ca 2**0
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CONTENTS, READONLY, DEBUGGING
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8 .debug_frame 00000064 00000000 00000000 00001834 2**2
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CONTENTS, READONLY, DEBUGGING
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9 .debug_str 00000463 00000000 00000000 00001898 2**0
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CONTENTS, READONLY, DEBUGGING
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10 .debug_loc 000000f4 00000000 00000000 00001cfb 2**0
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CONTENTS, READONLY, DEBUGGING
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11 .debug_ranges 00000030 00000000 00000000 00001def 2**0
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CONTENTS, READONLY, DEBUGGING
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Disassembly of section .text:
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00000000 <__vectors>:
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0: 45 c0 rjmp .+138 ; 0x8c <__ctors_end>
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2: 00 00 nop
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4: 4b c0 rjmp .+150 ; 0x9c <__bad_interrupt>
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6: 00 00 nop
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8: 49 c0 rjmp .+146 ; 0x9c <__bad_interrupt>
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a: 00 00 nop
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c: 47 c0 rjmp .+142 ; 0x9c <__bad_interrupt>
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e: 00 00 nop
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10: 45 c0 rjmp .+138 ; 0x9c <__bad_interrupt>
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12: 00 00 nop
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14: 43 c0 rjmp .+134 ; 0x9c <__bad_interrupt>
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16: 00 00 nop
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18: 41 c0 rjmp .+130 ; 0x9c <__bad_interrupt>
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1a: 00 00 nop
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1c: 3f c0 rjmp .+126 ; 0x9c <__bad_interrupt>
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1e: 00 00 nop
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20: 3d c0 rjmp .+122 ; 0x9c <__bad_interrupt>
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22: 00 00 nop
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24: 3b c0 rjmp .+118 ; 0x9c <__bad_interrupt>
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26: 00 00 nop
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28: 39 c0 rjmp .+114 ; 0x9c <__bad_interrupt>
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2a: 00 00 nop
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2c: 37 c0 rjmp .+110 ; 0x9c <__bad_interrupt>
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2e: 00 00 nop
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30: 35 c0 rjmp .+106 ; 0x9c <__bad_interrupt>
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32: 00 00 nop
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34: 33 c0 rjmp .+102 ; 0x9c <__bad_interrupt>
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36: 00 00 nop
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38: 31 c0 rjmp .+98 ; 0x9c <__bad_interrupt>
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3a: 00 00 nop
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3c: 2f c0 rjmp .+94 ; 0x9c <__bad_interrupt>
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3e: 00 00 nop
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40: 2d c0 rjmp .+90 ; 0x9c <__bad_interrupt>
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42: 00 00 nop
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44: 2b c0 rjmp .+86 ; 0x9c <__bad_interrupt>
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46: 00 00 nop
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48: 29 c0 rjmp .+82 ; 0x9c <__bad_interrupt>
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4a: 00 00 nop
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4c: 27 c0 rjmp .+78 ; 0x9c <__bad_interrupt>
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4e: 00 00 nop
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50: 25 c0 rjmp .+74 ; 0x9c <__bad_interrupt>
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52: 00 00 nop
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54: 23 c0 rjmp .+70 ; 0x9c <__bad_interrupt>
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56: 00 00 nop
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58: 21 c0 rjmp .+66 ; 0x9c <__bad_interrupt>
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5a: 00 00 nop
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5c: 1f c0 rjmp .+62 ; 0x9c <__bad_interrupt>
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5e: 00 00 nop
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60: 1d c0 rjmp .+58 ; 0x9c <__bad_interrupt>
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62: 00 00 nop
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64: 1b c0 rjmp .+54 ; 0x9c <__bad_interrupt>
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66: 00 00 nop
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68: 19 c0 rjmp .+50 ; 0x9c <__bad_interrupt>
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6a: 00 00 nop
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6c: 17 c0 rjmp .+46 ; 0x9c <__bad_interrupt>
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6e: 00 00 nop
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70: 15 c0 rjmp .+42 ; 0x9c <__bad_interrupt>
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72: 00 00 nop
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74: 13 c0 rjmp .+38 ; 0x9c <__bad_interrupt>
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76: 00 00 nop
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78: 11 c0 rjmp .+34 ; 0x9c <__bad_interrupt>
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7a: 00 00 nop
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7c: 0f c0 rjmp .+30 ; 0x9c <__bad_interrupt>
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7e: 00 00 nop
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80: 0d c0 rjmp .+26 ; 0x9c <__bad_interrupt>
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82: 00 00 nop
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84: 0b c0 rjmp .+22 ; 0x9c <__bad_interrupt>
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86: 00 00 nop
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88: 09 c0 rjmp .+18 ; 0x9c <__bad_interrupt>
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...
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0000008c <__ctors_end>:
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8c: 11 24 eor r1, r1
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8e: 1f be out 0x3f, r1 ; 63
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90: cf ef ldi r28, 0xFF ; 255
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92: d0 e1 ldi r29, 0x10 ; 16
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94: de bf out 0x3e, r29 ; 62
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96: cd bf out 0x3d, r28 ; 61
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98: 40 d0 rcall .+128 ; 0x11a <main>
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9a: 48 c0 rjmp .+144 ; 0x12c <_exit>
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0000009c <__bad_interrupt>:
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9c: b1 cf rjmp .-158 ; 0x0 <__vectors>
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0000009e <wait>:
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//is active low (refer to datasheet)
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void wait( int ms )
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{
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for (int i=0; i<ms; i++)
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9e: 20 e0 ldi r18, 0x00 ; 0
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a0: 30 e0 ldi r19, 0x00 ; 0
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a2: 08 c0 rjmp .+16 ; 0xb4 <wait+0x16>
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#else
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//round up by default
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__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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a4: e3 ec ldi r30, 0xC3 ; 195
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a6: f9 e0 ldi r31, 0x09 ; 9
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a8: 31 97 sbiw r30, 0x01 ; 1
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aa: f1 f7 brne .-4 ; 0xa8 <wait+0xa>
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ac: 00 c0 rjmp .+0 ; 0xae <wait+0x10>
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ae: 00 00 nop
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b0: 2f 5f subi r18, 0xFF ; 255
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b2: 3f 4f sbci r19, 0xFF ; 255
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b4: 28 17 cp r18, r24
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b6: 39 07 cpc r19, r25
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b8: ac f3 brlt .-22 ; 0xa4 <wait+0x6>
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{
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_delay_ms( 1 ); // library function (max 30 ms at 8MHz)
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}
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}
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ba: 08 95 ret
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000000bc <trigger>:
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void trigger()
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{
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CONTROLPORT |= GLCD_EN; //EN high
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bc: 88 b3 in r24, 0x18 ; 24
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be: 80 62 ori r24, 0x20 ; 32
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c0: 88 bb out 0x18, r24 ; 24
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#else
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//round up by default
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__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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c2: 81 e2 ldi r24, 0x21 ; 33
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c4: 8a 95 dec r24
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c6: f1 f7 brne .-4 ; 0xc4 <trigger+0x8>
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c8: 00 00 nop
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_delay_us(E_DELAY);
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CONTROLPORT &= ~GLCD_EN; //EN low
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ca: 88 b3 in r24, 0x18 ; 24
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cc: 8f 7d andi r24, 0xDF ; 223
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ce: 88 bb out 0x18, r24 ; 24
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d0: 81 e2 ldi r24, 0x21 ; 33
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d2: 8a 95 dec r24
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d4: f1 f7 brne .-4 ; 0xd2 <trigger+0x16>
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d6: 00 00 nop
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d8: 08 95 ret
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000000da <glcd_on>:
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}
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//----------------------
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void glcd_on()
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{
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#ifdef GLCD_CS_ACTIVE_LOW
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CONTROLPORT &= ~CS1; //Activate both chips
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da: 88 b3 in r24, 0x18 ; 24
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dc: 8e 7f andi r24, 0xFE ; 254
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de: 88 bb out 0x18, r24 ; 24
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CONTROLPORT &= ~CS2;
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e0: 88 b3 in r24, 0x18 ; 24
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e2: 8d 7f andi r24, 0xFD ; 253
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e4: 88 bb out 0x18, r24 ; 24
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#else
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CONTROLPORT |= CS1; //Activate both chips
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CONTROLPORT |= CS2;
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#endif
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CONTROLPORT &= ~GLCD_RS; //RS low --> command
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e6: 88 b3 in r24, 0x18 ; 24
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e8: 8b 7f andi r24, 0xFB ; 251
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ea: 88 bb out 0x18, r24 ; 24
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CONTROLPORT &= ~GLCD_RW; //RW low --> write
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ec: 88 b3 in r24, 0x18 ; 24
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ee: 87 7f andi r24, 0xF7 ; 247
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f0: 88 bb out 0x18, r24 ; 24
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DATAPORT = 0x3F; //ON command
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f2: 8f e3 ldi r24, 0x3F ; 63
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f4: 85 bb out 0x15, r24 ; 21
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trigger();
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f6: e2 cf rjmp .-60 ; 0xbc <trigger>
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f8: 08 95 ret
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000000fa <glcd_off>:
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}
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//----------------------
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void glcd_off()
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{
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#ifdef GLCD_CS_ACTIVE_LOW
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CONTROLPORT &= ~CS1; //Activate both chips
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fa: 88 b3 in r24, 0x18 ; 24
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fc: 8e 7f andi r24, 0xFE ; 254
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fe: 88 bb out 0x18, r24 ; 24
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CONTROLPORT &= ~CS2;
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100: 88 b3 in r24, 0x18 ; 24
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102: 8d 7f andi r24, 0xFD ; 253
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104: 88 bb out 0x18, r24 ; 24
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#else
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CONTROLPORT |= CS1; //Activate both chips
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CONTROLPORT |= CS2;
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#endif
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CONTROLPORT &= ~GLCD_RS; //DI low --> command
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106: 88 b3 in r24, 0x18 ; 24
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108: 8b 7f andi r24, 0xFB ; 251
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10a: 88 bb out 0x18, r24 ; 24
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CONTROLPORT &= ~GLCD_RW; //RW low --> write
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10c: 88 b3 in r24, 0x18 ; 24
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10e: 87 7f andi r24, 0xF7 ; 247
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110: 88 bb out 0x18, r24 ; 24
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DATAPORT = 0x3E; //OFF command
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112: 8e e3 ldi r24, 0x3E ; 62
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114: 85 bb out 0x15, r24 ; 21
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trigger();
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116: d2 cf rjmp .-92 ; 0xbc <trigger>
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118: 08 95 ret
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0000011a <main>:
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int main(void)
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{
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while (1)
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{
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glcd_on();
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11a: df df rcall .-66 ; 0xda <glcd_on>
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wait(2000);
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11c: 80 ed ldi r24, 0xD0 ; 208
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11e: 97 e0 ldi r25, 0x07 ; 7
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glcd_off();
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120: be df rcall .-132 ; 0x9e <wait>
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wait(2000);
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122: eb df rcall .-42 ; 0xfa <glcd_off>
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124: 80 ed ldi r24, 0xD0 ; 208
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126: 97 e0 ldi r25, 0x07 ; 7
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128: ba df rcall .-140 ; 0x9e <wait>
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12a: f7 cf rjmp .-18 ; 0x11a <main>
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0000012c <_exit>:
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12c: f8 94 cli
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0000012e <__stop_program>:
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12e: ff cf rjmp .-2 ; 0x12e <__stop_program>
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