opdracht 2.5 probeersel
This commit is contained in:
@@ -1 +0,0 @@
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:00000001FF
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@@ -1,227 +0,0 @@
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opdracht 2.1.elf: file format elf32-avr
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .data 00000000 00800100 00800100 0000017c 2**0
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ALLOC, LOAD, DATA
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1 .text 000000a4 00000000 00000000 00000054 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .comment 0000002f 00000000 00000000 0000017c 2**0
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CONTENTS, READONLY
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3 .debug_aranges 00000038 00000000 00000000 000001ab 2**0
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CONTENTS, READONLY, DEBUGGING
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4 .debug_info 00000b2a 00000000 00000000 000001e3 2**0
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CONTENTS, READONLY, DEBUGGING
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5 .debug_abbrev 00000830 00000000 00000000 00000d0d 2**0
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CONTENTS, READONLY, DEBUGGING
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6 .debug_line 000002cb 00000000 00000000 0000153d 2**0
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CONTENTS, READONLY, DEBUGGING
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7 .debug_frame 00000074 00000000 00000000 00001808 2**2
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CONTENTS, READONLY, DEBUGGING
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8 .debug_str 0000027d 00000000 00000000 0000187c 2**0
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CONTENTS, READONLY, DEBUGGING
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9 .debug_loc 000000e2 00000000 00000000 00001af9 2**0
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CONTENTS, READONLY, DEBUGGING
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10 .debug_ranges 00000028 00000000 00000000 00001bdb 2**0
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CONTENTS, READONLY, DEBUGGING
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11 .text 00000004 00000124 00000124 00000178 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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12 .note.gnu.avr.deviceinfo 0000003c 00000000 00000000 00001c04 2**2
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CONTENTS, READONLY, DEBUGGING
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13 .text.wait 0000001e 000000ca 000000ca 0000011e 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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14 .text.__vector_1 0000001e 000000e8 000000e8 0000013c 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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15 .text.__vector_2 0000001e 00000106 00000106 0000015a 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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16 .text.main 00000026 000000a4 000000a4 000000f8 2**1
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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Disassembly of section .text:
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00000000 <__vectors>:
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0: 0c 94 46 00 jmp 0x8c ; 0x8c <__ctors_end>
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4: 0c 94 74 00 jmp 0xe8 ; 0xe8 <__vector_1>
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8: 0c 94 83 00 jmp 0x106 ; 0x106 <__vector_2>
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c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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10: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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14: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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18: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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1c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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20: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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24: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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28: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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2c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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30: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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34: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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38: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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3c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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40: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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44: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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48: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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4c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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50: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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54: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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58: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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5c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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60: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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64: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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68: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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6c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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70: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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74: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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78: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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7c: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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80: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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84: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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88: 0c 94 92 00 jmp 0x124 ; 0x124 <__bad_interrupt>
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0000008c <__ctors_end>:
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8c: 11 24 eor r1, r1
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8e: 1f be out 0x3f, r1 ; 63
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90: cf ef ldi r28, 0xFF ; 255
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92: d0 e1 ldi r29, 0x10 ; 16
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94: de bf out 0x3e, r29 ; 62
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96: cd bf out 0x3d, r28 ; 61
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98: 0e 94 52 00 call 0xa4 ; 0xa4 <_etext>
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9c: 0c 94 50 00 jmp 0xa0 ; 0xa0 <_exit>
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000000a0 <_exit>:
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a0: f8 94 cli
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000000a2 <__stop_program>:
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a2: ff cf rjmp .-2 ; 0xa2 <__stop_program>
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Disassembly of section .text:
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00000124 <__bad_interrupt>:
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124: 0c 94 00 00 jmp 0 ; 0x0 <__TEXT_REGION_ORIGIN__>
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Disassembly of section .text.wait:
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000000ca <wait>:
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clock value is set. This is used by _delay_ms inside
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util/delay.h
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Version : DMK, Initial code
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*******************************************************************/
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void wait( int ms ) {
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for (int i=0; i<ms; i++) {
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ca: 20 e0 ldi r18, 0x00 ; 0
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cc: 30 e0 ldi r19, 0x00 ; 0
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ce: 08 c0 rjmp .+16 ; 0xe0 <wait+0x16>
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#else
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//round up by default
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__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
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#endif
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__builtin_avr_delay_cycles(__ticks_dc);
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d0: ef ec ldi r30, 0xCF ; 207
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d2: f7 e0 ldi r31, 0x07 ; 7
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d4: 31 97 sbiw r30, 0x01 ; 1
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d6: f1 f7 brne .-4 ; 0xd4 <wait+0xa>
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d8: 00 c0 rjmp .+0 ; 0xda <wait+0x10>
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da: 00 00 nop
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dc: 2f 5f subi r18, 0xFF ; 255
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de: 3f 4f sbci r19, 0xFF ; 255
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e0: 28 17 cp r18, r24
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e2: 39 07 cpc r19, r25
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e4: ac f3 brlt .-22 ; 0xd0 <wait+0x6>
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_delay_ms( 1 ); // library function (max 30 ms at 8MHz)
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}
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}
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e6: 08 95 ret
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Disassembly of section .text.__vector_1:
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000000e8 <__vector_1>:
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inputs:
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outputs:
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notes: Set PORTD.5
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Version : DMK, Initial code
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*******************************************************************/
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ISR( INT0_vect ) {
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e8: 1f 92 push r1
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ea: 0f 92 push r0
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ec: 0f b6 in r0, 0x3f ; 63
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ee: 0f 92 push r0
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f0: 11 24 eor r1, r1
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f2: 8f 93 push r24
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PORTD |= (1<<5);
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f4: 82 b3 in r24, 0x12 ; 18
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f6: 80 62 ori r24, 0x20 ; 32
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f8: 82 bb out 0x12, r24 ; 18
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}
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fa: 8f 91 pop r24
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fc: 0f 90 pop r0
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fe: 0f be out 0x3f, r0 ; 63
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100: 0f 90 pop r0
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102: 1f 90 pop r1
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104: 18 95 reti
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Disassembly of section .text.__vector_2:
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00000106 <__vector_2>:
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inputs:
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outputs:
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notes: Clear PORTD.5
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Version : DMK, Initial code
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*******************************************************************/
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ISR( INT1_vect ) {
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106: 1f 92 push r1
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108: 0f 92 push r0
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10a: 0f b6 in r0, 0x3f ; 63
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10c: 0f 92 push r0
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10e: 11 24 eor r1, r1
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110: 8f 93 push r24
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PORTD &= ~(1<<5);
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112: 82 b3 in r24, 0x12 ; 18
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114: 8f 7d andi r24, 0xDF ; 223
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116: 82 bb out 0x12, r24 ; 18
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}
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118: 8f 91 pop r24
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11a: 0f 90 pop r0
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11c: 0f be out 0x3f, r0 ; 63
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11e: 0f 90 pop r0
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120: 1f 90 pop r1
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122: 18 95 reti
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Disassembly of section .text.main:
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000000a4 <main>:
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notes: Slow background task after init ISR
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Version : DMK, Initial code
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*******************************************************************/
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int main( void ) {
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// Init I/O
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DDRD = 0xF0; // PORTD(7:4) output, PORTD(3:0) input
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a4: 80 ef ldi r24, 0xF0 ; 240
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a6: 81 bb out 0x11, r24 ; 17
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// Init Interrupt hardware
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EICRA |= 0x0B; // INT1 falling edge, INT0 rising edge
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a8: ea e6 ldi r30, 0x6A ; 106
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aa: f0 e0 ldi r31, 0x00 ; 0
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ac: 80 81 ld r24, Z
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ae: 8b 60 ori r24, 0x0B ; 11
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b0: 80 83 st Z, r24
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EIMSK |= 0x03; // Enable INT1 & INT0
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b2: 89 b7 in r24, 0x39 ; 57
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b4: 83 60 ori r24, 0x03 ; 3
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b6: 89 bf out 0x39, r24 ; 57
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// Enable global interrupt system
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//SREG = 0x80; // Of direct via SREG of via wrapper
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sei();
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b8: 78 94 sei
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while (1) {
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PORTD ^= (1<<7); // Toggle PORTD.7
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ba: 82 b3 in r24, 0x12 ; 18
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bc: 80 58 subi r24, 0x80 ; 128
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be: 82 bb out 0x12, r24 ; 18
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wait( 500 );
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c0: 84 ef ldi r24, 0xF4 ; 244
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c2: 91 e0 ldi r25, 0x01 ; 1
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c4: 0e 94 65 00 call 0xca ; 0xca <wait>
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c8: f8 cf rjmp .-16 ; 0xba <main+0x16>
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