mirror of
https://github.com/SemvdH/OBD2-car-display.git
synced 2025-12-15 04:01:04 +00:00
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
#include "sam3xa/include/component/component_tc.h"
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#include "obd2_timer.h"
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void obd2_RTT_init(void)
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{
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/* enable the timer: reset the RTT
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RTT->RTT_MR = RTT_MR_RTTRST;
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/* set the alarm value to 0*/
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RTT->RTT_AR = 0;
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}
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void obd2_RTT_enable()
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{
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/* enable the alarm interrupt and set the prescaler to the processor frequency to generate an interrupt every second*/
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RTT->RTT_MR |= RTT_MR_ALMIEN | RTT_MR_RTPRES(CLOCK_FREQ);
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/* enable the interrupt*/
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NVIC_EnableIRQ(RTT_IRQn);
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}
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void obd2_RTT_reset()
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{
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/* To prevent several executions of the interrupt handler,
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the interrupt must be disabled in the interrupt handler
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and re-enabled when the status register is cleared.
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*/
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/* disable interrupts */
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RTT->RTT_MR &= ~RTT_MR_ALMIEN;
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/* clear the status register (reading it clears it)
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SAM3X datasheet section 13.4: Reading the RTT_SR status register resets the RTTINC and ALMS fields.
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*/
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RTT->RTT_SR;
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/* set the alarm value to 0*/
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RTT->RTT_AR = 0;
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/* re-enable the interrupt*/
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RTT->RTT_MR |= RTT_MR_ALMIEN;
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/* reset the RTT*/
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RTT->RTT_MR |= RTT_MR_RTTRST;
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}
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void obd2_RTT_set_period(__UINT32_TYPE__ period)
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{
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/* set the prescaler value equal to the clock speed divided by how many milliseconds*/
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RTT->RTT_MR |= RTT_MR_RTPRES(CLOCK_FREQ / (1000/period));
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}
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void obd2_TC_init()
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{
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/* disable write protection */
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pmc_set_writeprotect(false);
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// /* set clock source to main clock */
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// pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
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/* set the clock to MCK/2, enable the timer/counter 0, enable RC compare trigger and capture mode */
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TC0->TC_CHANNEL[0].TC_CCR |= TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CCR_CLKEN | TC_CMR_CPCTRG & ~(TC_CMR_WAVE);
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/* disable the quadrature decoder, to route the IO pins of TIOA and TIOB directly to the timer counter function (36.6.14.1) */
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TC0->TC_BMR &= ~(TC_BMR_QDEN);
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}
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void obd2_TC_start()
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{
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/* software trigger the timer reset it and start the clock */
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TC0->TC_CHANNEL[0].TC_CCR |= TC_CCR_SWTRG;
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}
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