#include "sam3xa/include/component/component_tc.h"
#include "obd2_timer.h"

void obd2_RTT_init(void)
{
  /* enable the timer: reset the RTT
  RTT->RTT_MR = RTT_MR_RTTRST;
  /* set the alarm value to 0*/
  RTT->RTT_AR = 0;
}

void obd2_RTT_enable()
{
  /* enable the alarm interrupt and set the prescaler to the processor frequency to generate an interrupt every second*/
  RTT->RTT_MR |= RTT_MR_ALMIEN | RTT_MR_RTPRES(CLOCK_FREQ);

  /* enable the interrupt*/
  NVIC_EnableIRQ(RTT_IRQn);
}

void obd2_RTT_reset()
{
  /* To prevent several executions of the interrupt handler,
   the interrupt must be disabled in the interrupt handler
   and re-enabled when the status register is cleared.
*/
  /* disable interrupts */
  RTT->RTT_MR &= ~RTT_MR_ALMIEN;
  /* clear the status register (reading it clears it)
    SAM3X datasheet section 13.4: Reading the RTT_SR status register resets the RTTINC and ALMS fields.
  */
  RTT->RTT_SR;
  /* set the alarm value to 0*/
  RTT->RTT_AR = 0;
  /* re-enable the interrupt*/
  RTT->RTT_MR |= RTT_MR_ALMIEN;
  /* reset the RTT*/
  RTT->RTT_MR |= RTT_MR_RTTRST;
}

void obd2_RTT_set_period(__UINT32_TYPE__ period)
{
  /* set the prescaler value equal to the clock speed divided by how many milliseconds*/
  RTT->RTT_MR |= RTT_MR_RTPRES(CLOCK_FREQ / (1000/period));
}

void obd2_TC_init()
{
  /* disable write protection */
  pmc_set_writeprotect(false);
  // /* set clock source to main clock */
  // pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
  /* set the clock to MCK/2, enable the timer/counter 0, enable RC compare trigger and capture mode */
  TC0->TC_CHANNEL[0].TC_CCR |= TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CCR_CLKEN | TC_CMR_CPCTRG & ~(TC_CMR_WAVE);
  /* disable the quadrature decoder, to route the IO pins of TIOA and TIOB directly to the timer counter function (36.6.14.1) */
  TC0->TC_BMR &= ~(TC_BMR_QDEN);
}

void obd2_TC_start()
{
  /* software trigger the timer reset it and start the clock */
  TC0->TC_CHANNEL[0].TC_CCR |= TC_CCR_SWTRG;
}