From 5e934a19f177bff4df935dd0f8bd1fa49973f75c Mon Sep 17 00:00:00 2001 From: Sem van der Hoeven Date: Fri, 3 Nov 2023 00:25:00 +0100 Subject: [PATCH] timer --- due_obd2/due_obd2.ino | 3 ++- due_obd2/obd2_timer.c | 8 ++++++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/due_obd2/due_obd2.ino b/due_obd2/due_obd2.ino index 00f7e71..b8e04c1 100644 --- a/due_obd2/due_obd2.ino +++ b/due_obd2/due_obd2.ino @@ -119,7 +119,8 @@ void setup() pinMode(LED_BUILTIN, OUTPUT); - obd2_RTT_init(); + obd2_TC_init(); + statemachine_register_state(&init_state, STATE_INIT); statemachine_register_state(&main_state, STATE_CAR_INFO); statemachine_init(); diff --git a/due_obd2/obd2_timer.c b/due_obd2/obd2_timer.c index 379ec62..5994e0b 100644 --- a/due_obd2/obd2_timer.c +++ b/due_obd2/obd2_timer.c @@ -46,8 +46,12 @@ void obd2_RTT_set_period(__UINT32_TYPE__ period) void obd2_TC_init() { - /* enable the timer/counter 0 */ - TC0->TC_CHANNEL[0].TC_CCR |= TC_CCR_CLKEN; + /* disable write protection */ + pmc_set_writeprotect(false); + // /* set clock source to main clock */ + // pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK); + /* set the clock to MCK/2, enable the timer/counter 0, enable RC compare trigger and capture mode */ + TC0->TC_CHANNEL[0].TC_CCR |= TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CCR_CLKEN | TC_CMR_CPCTRG & ~(TC_CMR_WAVE); /* disable the quadrature decoder, to route the IO pins of TIOA and TIOB directly to the timer counter function (36.6.14.1) */ TC0->TC_BMR &= ~(TC_BMR_QDEN); }