mirror of
https://github.com/SemvdH/OBD2-car-display.git
synced 2025-12-16 04:31:04 +00:00
stuff
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@@ -1,4 +1,4 @@
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#include "sam3xa/include/component/component_tc.h"
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// #include "sam3xa/include/component/component_tc.h"
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#include "obd2_timer.h"
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void obd2_RTT_init(void)
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@@ -50,14 +50,48 @@ void obd2_TC_init()
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pmc_set_writeprotect(false);
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// /* set clock source to main clock */
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// pmc_mck_set_source(PMC_MCKR_CSS_MAIN_CLK);
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/* set the clock to MCK/2, enable the timer/counter 0, enable RC compare trigger and capture mode */
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TC0->TC_CHANNEL[0].TC_CCR |= TC_CMR_TCCLKS_TIMER_CLOCK1 | TC_CCR_CLKEN | TC_CMR_CPCTRG & ~(TC_CMR_WAVE);
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/* Enable peripheral clock */
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pmc_enable_periph_clk(TC0_IRQn);
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/* Disable clock (from arduino15/packages/arduino/hardware/sam/1.6.12/system/libsam/source/tc.c))*/
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TC0->TC_CHANNEL[0].TC_CCR = TC_CCR_CLKDIS;
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/* Disable interrupts*/
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TC0->TC_CHANNEL[0].TC_IDR = 0xFFFFFFFF;
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/* Clear status register by reading it*/
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TC0->TC_CHANNEL[0].TC_SR;
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/* disable the quadrature decoder, to route the IO pins of TIOA and TIOB directly to the timer counter function (36.6.14.1) */
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TC0->TC_BMR &= ~(TC_BMR_QDEN);
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// TC0->TC_BMR &= ~(TC_BMR_QDEN);
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/* Set wave mode to UP mode with automatic trigger, select wave mode, set the clock to MCK / 2*/
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TC0->TC_CHANNEL[0].TC_CMR = TC_CMR_WAVSEL_UP_RC | TC_CMR_WAVE | TC_CMR_TCCLKS_TIMER_CLOCK1;
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/* Enable the RC Compare interrupt*/
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TC0->TC_CHANNEL[0].TC_IER = TC_IER_CPCS;
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/* Disable all other interrupts */
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TC0->TC_CHANNEL[0].TC_IDR = ~TC_IER_CPCS;
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}
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void obd2_TC_set_RC_value(__UINT32_TYPE__ value)
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{
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TC0->TC_CHANNEL[0].TC_RC = TC_RC_RC(value);
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}
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void obd2_TC_start()
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{
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/* software trigger the timer reset it and start the clock */
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TC0->TC_CHANNEL[0].TC_CCR |= TC_CCR_SWTRG;
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/* Clear any still pending IRQs */
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NVIC_ClearPendingIRQ(TC0_IRQn);
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/* Enable the IRQ */
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NVIC_EnableIRQ(TC0_IRQn);
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/* software trigger the timer resets it and start the clock, also enable the clock */
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TC0->TC_CHANNEL[0].TC_CCR = TC_CCR_SWTRG | TC_CCR_CLKEN;
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}
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void obd2_TC_stop()
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{
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/* stop the clock using an RB load event in capture mode e (LDBSTOP = 1 in TC_CMR (datasheet 36.6.4) */
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// TC0->TC_CHANNEL[0].TC_CMR |= TC_CMR_CPCSTOP;
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/* Disable the clock*/
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TC0->TC_CHANNEL[0].TC_CCR = TC_CCR_CLKDIS;
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}
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